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ASU MAT 591: Opportunities in Industry!  

ASU MAT 591: Opportunities In Industry! 

Subject: On-board Processing 

By

Eric Smith

Lockheed Martin- Management and Data Systems

 


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ASU MAT 591: Opportunities in Industry!  

Presentation Overview 

  • Background
    • Quick overview of SAR
  • High level technical overview
    • Architectural Model
    • Hardware
    • Software
    • Issues
  • Applications
  • Related topics

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ASU MAT 591: Opportunities in Industry!  

GFLOPS in Space! 

OBP Goal:

> 100 GFLOPS

< 1 KW

< 100 KG 

Space-based Radar Notional Satellite


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ASU MAT 591: Opportunities in Industry!  

BACKGROUND


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ASU MAT 591: Opportunities in Industry!  

The need for imaging satellites capable of continuous coverage and real-time output products require high performance on-board processing 

Why On-Board Processing? 

  • Sensor control
    • Adaptive controls to improve sensor performance (e.g. ECCM / beamforming, adaptive optics)
  • Timely delivery of intelligence / dynamic re-tasking
    • Direct down link assures low latency and enables direct control by a tactical commander
    • Physical antenna size precludes ultra-wide bandwidth communications link
    • OBP required to reduce information bandwidth

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ASU MAT 591: Opportunities in Industry!  

OBP Applications 

  • SAR- Synthetic Aperture Radar
    • Requires significant computational resources to form SAR images
      • ~3500 operations per pixel

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ASU MAT 591: Opportunities in Industry!  

Example SAR Imagery


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ASU MAT 591: Opportunities in Industry!  

Example SAR Imagery


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ASU MAT 591: Opportunities in Industry!  

OBP Applications 

  • SMTI- Surface moving target indication
    • Radar application similar to SAR which is used to distinguish moving targets for from the fixed background scene
    • Collect times are fractions of a second long
    • Requires combination of DSP and linear algebra to create adaptive algorithms needed to separate the movers for scene
  • Metrology/Controls processing 
     
     
     
    • Determining the motion of a structure so as to correct for the induced phase errors
    • Integral part of a control system; very sensitive to latency
  • Others��
 

Moving Target Indicator


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ASU MAT 591: Opportunities in Industry!  

Architecture Overview


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ASU MAT 591: Opportunities in Industry!  

Factors Driving an OBP Architecture 

Algorithm/Application Requirements

  • Effective Flops requirement
  • Memory capacity and  
    bandwidth
 

Environment

  • Radiation
  • Available Cooling
 

SV Constraints

  • Size
  • Weight
  • Operating Power
 

Risk Factors

  • Schedule
  • Cost
 

Mission Life

  • Design Life
  • Reliability
 

Life Cycle Cost

  • NRE and Recurring
  • O&M and upgrades
 

OBP  
Architecture


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ASU MAT 591: Opportunities in Industry!  

OBP Architecture 

MUX Mod  

Processing

Element #1 

Processing

Element #n 

MUX

Fabric 

NVMS 

Control Proc 

NVMS 

Control Proc 

cPCI 

Bus Computer 

UART 

LLP 

LLP 

LLP 

Output

Formatter 

LLP 

MEM Slice #1 

MEM Slice #n 

LLP 

LLP 

  • Link Level Protocol (LLP)
  • 800 MBps
 

From

Sensor 

To Comm(s) 

Mass

Data Storage 

Network Fabric 

PE��s and Control Proc��s


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ASU MAT 591: Opportunities in Industry!  

OBP Architectural Concepts 

  • Modular architecture with separate module types
    • Network infrastructure
    • Mass data storage
    • Processing elements
      • Sensor data processing elements
      • Control/general purpose processing elements
    • IO Subsystem
  • Processor configured as needed for the application
    • Mix of module types is determined by requirements
      • Performance
      • Functionality
      • Availability- N+1 versus 2N redundancy

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ASU MAT 591: Opportunities in Industry!  

Representative Performance Requirements 

  • Performance Specifications
    • Processing Elements
      • 24 Gflops per Processing Module (PM )
      • 56 watts
      • 1 Gbyte/PE
    • MDS
      • 64 Gbits/slice
      • 30 watts/slice
    • Network
      • 8x800MBps simultaneous input channels
      • 16 PE maximum
  • SBR Configuration Requirements
    • 240 Gflops scalable to 384 Gflops for Back End Processor (BEP)
    • ½ Tbit
    • 1400watts (w/ margin)
    • Post-mitigation Single Event Upset (SEU) Rate
      • 0.06 bit errors / hour
    • Total Ionization Dosage (TID) Tolerance
      • greater than 75 Mev*cm2/mg

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ASU MAT 591: Opportunities in Industry!  

H/W Architectures


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ASU MAT 591: Opportunities in Industry!  

Approach 

Continuum of Computational Alternatives 

Performance 

Flexibility 

ASPs 

GP

Microprocessors 

PowerPC, x86 

LSP, LSP-II 

FPGA 

Commercial

DSP 

TI, Analog Device, TriMedia 

Xilinx, Atmel 

  • Benefit from high volume /commodity production
 
  • Well understood HOL programming model,

robust set of commercially supported tools 

  • Relative poor domain specific performance
 
  • Large recurring technology investment
 
  • Low level or HDL based programming

homegrown/custom tools required 

  • Excellent domain specific performance
 

Full Custom 

LL beamformer


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ASU MAT 591: Opportunities in Industry!  

FLOP/Watt Performance Comparison 

Peak MFlops (MOp) /Watt for large FFT in 2002 

GP + FPGA

390 

GP + LSPII

425 

Comm

PPC G4

118 

Rad

PPC 750

7 

Near Future

1430 

1 

10 

100 

1000 

SBR LEO Threshold 

GP + FPGA/RCC

120 

Wideband Processing 

Maxwell

SCS750

23 

Narrowband/General Purpose Processing


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ASU MAT 591: Opportunities in Industry!  

Processing Element Trade Data 

Fixed point  

MF/W at the

chip level

based on a

256K FFT 

Power at the

chip level 

Estimate


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ASU MAT 591: Opportunities in Industry!  

Background: FPGA 

  • FPGA: Field Programmable Gate Array
    • Logic device whose configuration can be set to meet the specific application requirement
      • Two types
        • RAM based can be reprogrammed in the field after deployment
        • Anti-fuse based devices can only be programmed once
    • Used for prototyping, low volume applications
    • Features
      • Embedded RAM, Multiplier Arrays, and Hard IP such as RISC cores
      • Current generation have the equivalent of a couple million logic gates
        • Next generation will have 10s of million logic gates
  • Basis for Reconfigurable Computing Paradigm

 


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ASU MAT 591: Opportunities in Industry!  

Example FPGA: Xilinx Vertex-II 

Conf

Logic

Block

Frames

(CLB) 

BRAM0 

BRAM1


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ASU MAT 591: Opportunities in Industry!  

Features of processing 

  • DSP for image formation
    • Complex arithmetic
      • Single precision floating-point or fixed point math
    • Linear shift-invariant operators
      • FFT
      • FIR filtering
    • Extremely high data/processing rates
      • 100��s of GFLOPS
  • Linear algebra for motion compensation and SMTI
    • Double precision
    • Exception handling
  • Heuristic & non-linear processing for backend processing
    • Includes ��pixel polishing�� and SMTI

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ASU MAT 591: Opportunities in Industry!  

Approach based on heritage systems  

Enhanced Parallel Vector Supercomputer 

Enhanced MPP Supercomputer


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ASU MAT 591: Opportunities in Industry!  

Reconfigurable Computing Paradigm 

  • Utilizes FPGAs or FPGA-like devices that can be configured in such a way that is ��optimal�� for a specific processing task
    • The meaning of ��optimal�� depends on the criteria
      • Fastest time-to-market
      • Highest throughput for the least amount of energy
  • Goal is to program these devices using standard S/W processes while achieving ��optimal�� performance
    • E.G. ��C�� to circuits using a GNU compiler
    • Lots of on-going research with promising results
      • JHDL  at BYU, Stream-C at LANL
      • FORGE tool by Xilinx
    • LM uses a combined Top Down/ Bottoms-up Methodology to achieve ��optimal�� performance based on highest FLOP/Watt criteria

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ASU MAT 591: Opportunities in Industry!  

Processing Element 

  • FPGA Based
    • Gate density/performance now permits system-on-chip complexity
      • Available with embedded RISC processors and other IP
      • I/O and chip package pin count limitations overcome by moving functions onto a single chip
    • Commercially supported tools and development environments
    • Avoids high NRE costs for advanced semiconductor processes
      • $1M+ mask charge in 90nm process
      • Higher risk
      • Requires Large on-going investment in a non-core competency
      • Availability of vendors for low volumes uncertain (ROA thing)
  • Overall programming model comparable with heritage systems
    • Differs at the low level programming step

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ASU MAT 591: Opportunities in Industry!  

Processing Element Module (PEM) 

  • User enabled TMR based SEU mitigation using RHBD FPGA
  • Maintains primitive /algorithm compatibility
  • GP control from external RHDB computer
  • 3 sections per module 
  • 22.5 Gflop/s peak throughput  
    (sustained for large FFTs)
     
  • 1 GByte shared memory 
  • 8 MByte local memory per section 
 

Acronyms

RHBD Rad-hard by design

TMR Triple modular redundancy 

PE 3 

Xilinx 

XC2V6000 

150MHz 

QDR SRAM 

256Kx72 

.9 watts: 1 chip 

7.5 Gflops 

11.6 watts 

650 Mflop/w 

PortA 

Config/ 

SEU 

110 

BufD 

PortB 

PortC 

110 

110 

QDR SRAM 

256Kx72 

.9 watts: 1 chip 

QDR SRAM 

256Kx72 

.9 watts: 1 chip 

QDR SRAM 

256Kx72 

.9 watts: 1 chip 

110 

BufC 

110 

BufA 

110 

BufB 

PE 2 

Xilinx 

XC2V6000 

150MHz 

QDR SRAM 

256Kx72 

.9 watts: 1 chip 

7.5 Gflops 

11.6 watts 

650 Mflop/w 

PortA 

Config/ 

SEU 

110 

BufD 

PortB 

PortC 

110 

110 

QDR SRAM 

256Kx72 

.9 watts: 1 chip 

QDR SRAM 

256Kx72 

.9 watts: 1 chip 

QDR SRAM 

256Kx72 

.9 watts: 1 chip 

110 

BufC 

110 

BufA 

110 

BufB 

PE 1 

Xilinx 

XC2V6000 

150MHz 

QDR SRAM 

256Kx72 

.9 watts: 1 chip 

7.5 Gflops 

11.6 watts 

650 Mflop/w 

PortA 

Config/ 

SEU 

110 

BufD 

PortB 

PortC 

110 

110 

QDR SRAM 

256Kx72 

.9 watts: 1 chip 

QDR SRAM 

256Kx72 

.9 watts: 1 chip 

QDR SRAM 

256Kx72 

.9 watts: 1 chip 

110 

BufC 

110 

BufA 

110 

BufB 

Interface

/ TMR Supervisor

(Actel RTAX2000S) 

40 

RapidIO

(8-bit) 

DATA STORAGE 

DDR SDRAM 

1 GBYTE 

12 Watts : 16 chip 

115 

22.5 Gigaflops 

51.8 watts (peak) 

367 Mflops/watt 

40 

10 

40 

10 

40 

10 

POWER CONVERTER 

70% efficient 

(22.2 Watts dissipated @ 51.8 Watt load) 

I/O=      345 

Power= 5 watts 

40 

RapidIO

(8-bit)


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ASU MAT 591: Opportunities in Industry!  

RCC Implementation Styles 

  • Two styles used by Lockheed Martin
    • Optimized ��Primitives��
      • Circuits are developed and specifically optimized for each operation type
        • E.G Fast Fourier Transform
        • Circuits developed using a h/w description language such as Verilog or VHDL
      • Collections of such circuits are implemented on a physical FPGA device
        • Routing between these circuits implement an algorithm
        • The FPGA is reconfigured as needed with different primitives to implement the overall algorithm
      • Issues
        • Can be used where reconfiguration time is not an issue
        • May require a large number of primitive types
    • Micro-coded Function Module Group
      • A few programmable state-machine based circuits are developed that can perform the processing required for a class of operation types
      • Multiple copies of such circuits are implemented and programmed separately for each task
      • Issues
        • Useful when configuration time is at issue
        • Typically less optimal

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ASU MAT 591: Opportunities in Industry!  

Example RCC Styles 

Micro-coded FMG 

Optimized Primitives


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ASU MAT 591: Opportunities in Industry!  

H/W Abstraction Layer 

  • Exposes germane implementation details to application developers
  • Standard API simplifies application development
    • Fosters re-use
    • Simplifies maintenance and spiral development
  • Provides a standard set of resources to the application partition
    • Infrastructure treated as fixed IP
      • Memory interface including address controller
      • External interface
      • Embedded controller

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ASU MAT 591: Opportunities in Industry!  

H/W Abstraction Layer 

ACF 

ACF 

ACF 

ACF 

Algorithm Partition Area

(algorithm partitions go here

External I/F 

QDR

Memory 

QDR

Memory 

QDR

Memory 

QDR

Memory 

To/From Control FPGA 

Fixed IP 

GP Controller


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ASU MAT 591: Opportunities in Industry!  

GP Controller 

MicroBlaze 32-bit RISC Core

  • Performs initialization, algorithm level sequencing and control, exception handling
  • Vendor supported tool suite and development H/W
    • GNU, VXWorks
  • 82 D-MIPS @ 125 MHz on Virtex-II (-5)
  • Instantiated Size (min): 900 cells (plus memory, peripherals)

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ASU MAT 591: Opportunities in Industry!  

FMG Approach 

  • Consists of the resources needed to implement required arithmetic operations
    • Arithmetic units, local memory, and local control
  • Used in conjunction with the H/W abstraction layer to implement primitives
    • Overall primitive control encapsulated in the API
      • Primitive operation uses global resources that are part of the HAL
    • Viewed by the application programmer as a library
  • High level control provided by on-board RISC controller

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ASU MAT 591: Opportunities in Industry!  

Generic FM Architecture Description 

  • Implements data path part of primitive functions
    • Used in conjunction with HAL/GP
  • Calls initiated by GP in ��C��
 

Local Memory 

Data Path 

Configuration Registers 

Initialization & Control 

Static & Dynamic

control 

Status 

Initialization 

Data In 

Data Out 

Condition

Codes 

FMG 

Microcode SM


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ASU MAT 591: Opportunities in Industry!  

Optimized Primitive: Radix-2 FFT 

Add 

Add 

Add 

Add 

Add 

Add 

Mpy 

Mpy 

Mpy 

Mpy 

Dly 

Out 

In 

Dly 

Fold 

Part: XC2V6000-5FF1152

Part Utilization: 10%  (overall)

Circumscribed Area Utilization: 20%

Flip flops = 11%

LUTs  =    7%

Slices   = 15%

BRAMs  =    6%

18x18 Mpy =  11%

Power = 2.4 watts

Speed (-5)  = 5.824 ns = 171 MHz 

QDR_BankA 

QDR_BankB 

Read Address Generator 

Timing & Control 

Write Address Generator 

Half Butterfly 

Output Multiplexer 

Half Butterfly 

Twiddle Generator


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ASU MAT 591: Opportunities in Industry!  

FFT Logic Placement Comparison 

QDR_BankA 
 
 

QDR_BankB 
 
 

Read Address

Generator 
 
 

Timing &

Control 
 
 

Write Address

Generator 
 
 

Add 

Add 

Add 

Add 

Add 

Add 

Mpy 

Mpy 

Mpy 

Mpy 

Dly 

Out 

In 

Dly 

Twiddle

Generator 
 
 

Output

Multiplexer 
 
 

Half

Butterfly 
 
 

Fold 
 
 

Half

Butterfly 
 
 

Manual placement 

Automatic placement 

Manual placement results in better overall device utilization, increased performance, and is more conducive to re-use


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ASU MAT 591: Opportunities in Industry!  

Algorithm Implementation Process


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ASU MAT 591: Opportunities in Industry!  

Example Processing Dataflow 

E

S

A 

Multi-Channel Receiver 

Offset A-to-D Converters 

Filter RF Subbands 

Delay and Equalize ESA Ch.s 

Form 4

GMTI Beams 

FEP: ��Front End�� Processing 

MDS 

Convert Fast Time to Frequency 

Correct Subbands 

Resample Polar VPH 

Compress Subbands to Range 

Turn Range to Slow Time 

Compress to Azimuth 

Background Sampling 

Multi_Algo Weights Calculations 

Suppress Clutter / Filter Velocities 

Turn Azimuth to Range 

Combine Subbands 

Compress Full - BW Pulses 

Multi_Algo Detectors & CFARs 

Multi-Algo NCI / 
CPI Combiners
 

Target Reports 

OBP: ��Back End�� Processing


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ASU MAT 591: Opportunities in Industry!  

Decomposition to primitives 

Convert Fast Time to Frequency 

Correct Subbands 

Compress to Azimuth 

Background Sampling 

Multi_Algo Weights Calculations 

Suppress Clutter / Filter Velocities 

Turn Azimuth to Range 

Combine Subbands 

Compress Full - BW Pulses 

Multi_Algo Detectors & CFARs 

Multi-Algo NCI / 
CPI Combiners
 

Target Reports 

Resample Polar VPH 

Compress Subbands to Range 

Turn Range to Slow Time 

  • Phase Training / Culling
  • Power Selected Training
  • Compute covariances
  • Perform 2_D smoothing
 
  • Eigen decomposition
  • Sample Matrix Inversion
  • Adaptive channel balance
 
  • Data Format Convert (DFC)
  • Mo-comp phase stabilization
  • Fast time to RF xform
 
  • Fast time sample adjust
  • Fresnel quadratic removal
  • Fresnel De-ripple
 
  • (bypassed in WAS mode)
 
  • (Staggers formation)
  • Azimuth weighting
  • Doppler vs. Rg sample shift in AZ
 



  • Apply weights
  • (Combine staggers)
  • Combine 4-to-3 beams
 
  • Incl ��Burn Through Clutter Discrimination

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ASU MAT 591: Opportunities in Industry!  

Algorithm Components 

    Chain: Sequence of Primitives- Programmed in HOL (��C��) 

    Primitive: A signal processing function (kernel) on the scale of a complete FFT or vector  filtering function 

    Examples: 



RFG 

Reference Function 
Generator
 

Complex Multiply 

FFT 

Fast 
Fourier 
Transform
 

Perform FFT on Signal Vector 

IPF 

In-Plane 
Filter
 

Filter the Complex Signal 

SQRT 

Square Root 

Take the Square Root of Real-valued samples 


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ASU MAT 591: Opportunities in Industry!  

Components of  a Primitive 

RISC Controller 

HAL 

API 

FMG 

FMG 

Configuration Registers 

Microcode SM 

Data Path 

Configuration Registers 

Device 

Device 

Device 

e.g. Vsma(v1, d1, x, v2, d2, d3, cnt) 

void Vsma(V *v1, int d1, double x,

     V *v2, int d2,

     V *v3, int d3, int cnt)

{ 

  // Init Address Generators

  *adr_src1_strt= v1;

  *adr_src1_inc=  d1;

  *adr_src2_strt= v2;

  *adr_src2_inc=  d2; 
 

  // Init FMG

  *fmg_c1= x;

  *mc_adr= Vsma;

  *mc_start= go;

}


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ASU MAT 591: Opportunities in Industry!  

Primitive Development Process 

  • Specify
    • Derive requirements
    • Develop test plan
  • Design
    • Create API
      • Create a high level model of the primitive in ��C��
    • Perform functional decomposition 
    • Create data flow
 
  • Implement
    • Write HOL interface
    • Write microcode
    • Simulate
    • Verify
  • Acceptance Test
  • Document
    • Update programmer��s guide
  • Signoff and Promote
    • Update primitive library

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ASU MAT 591: Opportunities in Industry!  

Implementation Flow 

Primitive Development

    • Bottom-up
      • Microcoded data path
      • Low-level initialization
 

Algorithm Prototyping &

     Implementation

  •   Matlab©
  •   Mathcad©
  •   HOL
 

Faster,

Harder,

more results��. 

Primitive Library Development

(Off-Line) 

Algorithm Development

    • Top-down
    • Canonical S/W development environment
    • Supports mixed environment
      • Workstation/PE
      • Allows rapid prototyping
 

Specification

Functional Prototype 

API

Primitive


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ASU MAT 591: Opportunities in Industry!  

Chain Development 

  • Environment supports mixed implementation of FPGA and workstation based functional prototype primitives
    • During development, chains implemented as individual calls to the PEM, possibly with FPGA reconfiguration between calls
  • Functional prototypes used as the specification for the FPGA implementation
 



DFC 

Deskew Phase 

        

Change 

FFT1 

RFG2A 

RFG2B 

FFT2 

Range Ripple 

      

Correction 



Data Format 

-1 

+1 

Synthetic Target 

   

Phase History 

    

Generator 

Emulation executed on the workstation


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ASU MAT 591: Opportunities in Industry!  

Development Testbench 

PEM 

Testbench 

Stimulus Data /Operating

Parameters 

Configuration Bit

Streams 

Results


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ASU MAT 591: Opportunities in Industry!  

Issues related to OBP


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ASU MAT 591: Opportunities in Industry!  

Issues: Radiation 

  • Two Basic Effects
    • TID- Total Ionizing Dose
      • The amount of ionizing radiation that a device can tolerate before it fails
      • Cumulative effect that is highly dependent on the orbit and mission duration
      • Devices that are able to withstand > 200KRads are considered radiation tolerant
      • Can be mitigated by shielding
      • Causes increased current flow possibly leading catastrophic device failure
    • Single event effects (SEE)
      • Effects typically caused by high energy particles which temporarily interrupt device operation
        • SEU-single event upsets
          • Cause registers/memory to change state resulting in incorrect results being generated
        • SEFI- single event functional interrupts
          • Causes the device to stop functioning until reset or power-cycled
      • SEEs rates are a function of the orbit, solar flare activity, and the device characteristics
        • Unaffected by shielding; requires active mitigation techniques to overcome

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ASU MAT 591: Opportunities in Industry!  

Radiation Environment  

  • LEO
    • TID post-shield 2.83E+03 (no margin)
    • SEU Effects
      • Heavy Ions Flux: at 30MeV-cm2/mg = 500E-06 
                                     at 80MeV-cm2/mg = 150E-06
      • Galactic  at 30MeV-cm2/mg = 500E-09 
        Cosmic Rays:  at 80MeV-cm2/mg = 150E-09
    • Orbit: 600 Km circular, 94�� inclination, 5 year
  • MEO
    • TID post-shield 67.0E+03 (no margin)
    • SEU Effects
      • Heavy Ions Flux: at 30MeV-cm2/mg = 500E-06 
         at 80MeV-cm2/mg = 150E-06
      • Galactic  at 30MeV-cm2/mg = 500E-09 
        Cosmic Rays:  at 80MeV-cm2/mg = 150E-09
    • Orbit: 10,000 Km circular, 94�� inclination, 5 year
 

Example Equatorial Orbit,5 Years, No SAA 

Orbital Altitude (1000 kilometers) 

1 

10 

100 

1000 

10,000 

krads 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

Commercial Component

Radiation Range


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ASU MAT 591: Opportunities in Industry!  

Latch-up 

  • Potentially catastrophic device failure mechanism that can be brought on by prolonged exposure to a radiation environment
  • Parasitic BJTs within MOS transistors and the existence of path for current flow can result in the creation of an ��induced�� Darlington-pair transistor (2 gain).
 

*Digital Integrated Circuits, by Jan M. Rabaey, Prentice Hall ��95


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ASU MAT 591: Opportunities in Industry!  

Raw Unmitigated 2V6000 Upset Rates 

  • 1000km, 90 degree inclination orbit, CREME96
    • GCR max – The solar-quiet ("no flare") model in CREME96 represents the ambient environment, which prevails in the absence of solar energetic particle ("flare") events. This environment, which varies slowly in intensity over the 22-year solar cycle, is the basic environment in which all space systems must operate.
    • Worst Week Day (WWD) – This model is based on SEP fluxes averaged over the 180 hours (=7.5 days) beginning at 1300 UT on 19 October 1989. This week was the most severe SEP environment observed in the last two solar maxima (roughly 1980.5-83.5 and 1989.0-92.0). It can therefore be used as a "99% worst case" environment for systems designed to operate through solar maximum.
    • Worst Day (WD) – This model is based on SEP fluxes averaged over 18 hours beginning at 1300 UT on 20 October 1989. This period was the single largest flux enhancement in October 1989. It was caused by the arrival at Earth of a powerful interplanetary shock, which also produced a large geomagnetic storm.

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ASU MAT 591: Opportunities in Industry!  

Raw 2V6000 Upset Rates 

  • Upsets in the CLBs dominate device upset rate

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ASU MAT 591: Opportunities in Industry!  

Mitigated Upset Rate 

  • Also considering the 1 in 10 functional error rate factor.
    • About 1 in 10 configuration errors results in a real functional error.
  • The mitigated upset rate .041 non-flare, 2.03 flare, per device/day

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ASU MAT 591: Opportunities in Industry!  

Approaches to SEU Mitigation 

  • Hard By Design
    • Use semiconductor technology and libraries that are inherently radiation hard
      • Few manufacturers
      • Older technologies that don��t meet SWaP (and performance) requirements
  • TMR- Triple Mode Redundancy
    • The ��Gold�� Standard
    • Uses majority voting to determine the correct output from a logic block
    • Expensive- Requires essentially 3x the amount of H/W to implement each function
  • Signature Analysis
    • Logic block stimulated with a known input; output checked to verify that the correct response is generated
    • Can be implemented with little overhead using CRC
    • May be difficult to generate stimuli that provides good circuit coverage

52  

ASU MAT 591: Opportunities in Industry!  

Other Approaches to SEU Mitigation 

  • Exploits characteristics of the algorithms to detect efforts
    • Consider the discrete Fourier transform and efficient implementations called fast Fourier transform
    • What do you know about the energy content of a signal on either side of the transform? 
       
       
       
 

FFT 

F() 

f(t) 

Parseval��s Theorem:


53  

ASU MAT 591: Opportunities in Industry!  

Issues: Mission Success 

  • Fault-tolerance / graceful degradation
    • The ability to continue to operate in the presence of faults perhaps at diminished capacity
    • Achieved thru robust design and verified thru extensive analysis and testing
      • Elimination of failure modes in which a single failed component could render the entire system non-operational
  • Approaches 
     
    • Redundancy
      • N+m- Incremental redundant functional
      • A/B Side- duplicated subsystems that are cross-strapped
    • Error Detection and Correction (EDAC)
      • Used extensively in memory and network subsystems
    • Reprogramming / Reconfiguration

54  

ASU MAT 591: Opportunities in Industry!  

Fault-tolerance 

Cross-strapping 

N+m 

  • Employs redundancy throughout
    • Memory and PE modules
    • Data paths
  • EDAC in memories and network
  • Reprogramability / Reconfigurability

 


55  

ASU MAT 591: Opportunities in Industry!  

In-flight changes 

Incorporate

Modification 

Data or

Code +

Config File

Uplink 

Test and

Integration 

Change

Analysis and

Correction 

Change

Detection 

OK 

OK 

Failure 

OBP 

OBP

Self Test 

Config

File

Uplink 

Test

Collection and

Processing 

TES 

Support Facility 

EDU 

Support Facility 

The process being used on an operational ground based system is directly applicable to the SBR program


56  

ASU MAT 591: Opportunities in Industry!  

Future Generation OBP


57  

ASU MAT 591: Opportunities in Industry!  

MEO Notional Design 

  • Nominal 100m x 9m AESA feed
  • 50 nominal phase center spacing
  • 400 channels (1.5m x 1.5m panels)
  • 5,000km (2,700 NM) - 15,000km (8,100 NM)
 

MEO SBR concept requires designers to re-think their approach: distributed processor architecture


58  

ASU MAT 591: Opportunities in Industry!  

Architectural Concept 

Enhanced fault-tolerance 

SM 



Versatile Processing Element (VPE) 

DSP

Engine 

f1 

DSP

Engine 

f2 

DSP

Engine 

f3 

LM 

LM 

Sensor Input 

100m 


VPE 

N/W I/F 

PPC405 

SM Ctl 

Combination of DSP engine hard macrocell and FPGA enable overall algorithm optimization 

Network of distributed processing elements reduces cost and improves fault-tolerance 

NIC 

OCC


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