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App plicatio n Note e MOS- -010

Page 1
Rev. 1.0
Abstract: Thi applications. examination
1. Introdu
MOSFETs w supplies and power applic improve effic Multiple facto parameters, unbalanced c MOSFETs. reaching dam gate of each MOSFETs by these issues
2. Unbala
Under steady across each. RDS(on) increa balance the current incre RDS(on). At th current sharin Under switch controlled sw imbalances, voltage, its f inductances the time of de matched para gate driver d properly bala
ing Pow
s paper discu It investigat of PCB layou
with low on-re motor driver cations, multip iency. ors influence asymmetric current flow i Second, the maging levels h MOSFET, c y exceeding and provides
anced Curr
y-state condit . The on-res ases with tem current amo eases in one at point, curre ng amongst t hing condition witch. During especially at forward trans in the PCB a evice product ameters can design techni anced.
wer MOS
usses issues tes root caus uts and import esistance and rs in e-bikes, ple MOSFETs successful pa gate drivers, in parallel MO drain-to-sourc s on the drain causing exce its maximum s recommend
rent and Vo
tions, parallel sistance (RDS mperature. ng multiple M MOSFET, p ent will flow to he MOSFETs ns, the story is g the dynam higher freque sconductance all factor in to tion and cann be economica ques that en
SFETs in
involved in pa se problems s tant circuit de d fast switch electric-moto s used in par aralleling of h and poor la OSFETs can ce voltage ap n of one of th essive gate-to m rated VGS. ed solutions.
oltage- in P
S(on)) of a MO
This known MOSFETs. ower dissipa o one of the o s. s very differe mic process o encies. The e, total gate current and not be change ally challengin nsure that the
n Switch
aralleling MO such as unba esign paramet hing characte or cars, power rallel are ofte high-speed po yout of the P provoke ove pplied to each he devices. o-source volt This applica
Parallel MO
s work well, s OSFET has a phenomenon Current flows tion also inc other MOSFE ent. Generally of switching, characteristic charge (Qg), voltage imba ed in the appl ng. The best e current and
hing App
OSFETs in hig alanced volta ters for drivin eristics are w r tools and el en necessary ower MOSFE PCB can cau er-current con h MOSFET c Finally, paras age, potentia tion note con
sharing curren positive tem n assists in s through the reases, heati Ts with a low y speaking, a many factor cs of the MOS RDS(on), the alances. The lication, and s t way to preve d voltage acr
n Note
gh-power, hig age and curre g paralleled M widely used in ectric lawn m to increase ETs. Varianc use a numbe nditions and can actually b sitic oscillatio ally damaging nducts a deta
nt with an eq mperature coe paralleling M e path of lea ing the devic wer resistance a MOSFET be rs can cause SFET, includi actual driver e MOSFET pa screening MO ent these prob ross the para
e MOS-
h-frequency s ent by taking MOSFETs. n switch-mod mowers. In th current capab ce in the actu er of problem damage one be different, p ons can appe g one or mor ailed study of ual amount o efficient, mea MOSFETs as ast resistance ce and increa e, causing the ehaves like a e current and ing the gate t r circuit and arameters are OSFETs to ge blems is to us alleled MOSF
age 1 of 8
r 2013
switching a closer de power hese high bility and al device ms. First, or more otentially ear at the re of the f each of of voltage ning that it helps e and as asing the e inherent a voltage- d voltage threshold parasitic e fixed at et exactly se proper FETs are

Page 2
Rev. 1.0
2.1. Current Understandin applications i Threshold Vo or gate driver second MOS the lower VGS Forward Tran off and the O voltage, VGS Different gate versa. Gate Charge current flow MOSFETs ar MOSFETs. T causing anot 2.2. The Effe In the gate d impact of m recommende these gate re are paralleled gate of Q2. T
on Note M
Unbalance R ng MOSFET is an importan oltage, Gate-t r signal. A M SFET with a s
S(TH) and an u
nsconductanc Ohmic region . This regio e-to-source v e (Qg): Total from drain-to re paralleled, This faster tu ther unbalanc ect of the Ga driver circuit s mismatched g ed in high-freq esistors are m d. R1 is the d This creates t F
Resulting Fro parameters a nt first step to to-Sourec (VG OSFET with a slightly higher nbalanced cu ce (gFS): In th where the M n is governe voltages will c gate charge, o-source, will if one of the urn on causes ced current co te Driver Res shown in figu gate resistan quency appli matched as cl driving resisto the gate drive Figure 1. Dri
om MOSFET and how they o determining
GS(TH)): Parall
a lower gate- r VGS(TH). This urrent situatio he saturation MOSFET is fu ed by the for cause curren the total cha significantly a MOSFETs h s that MOSFE ondition. sistance on ure 1, an inte nces. As w cations to av osely as poss or connected er mismatch. ving Circuit
T Parameters y affect curren the right solu leled MOSFE to-source thre s results in h n. region betwe ully on, the d rward transco nt imbalances arge required affect the sw has a lower Q ET to handle Current Imba ntional mism will be shown void additiona sible. In the g in series with with the Gat s nt and voltage ution to the pr ETs are norma eshold voltag igher current een the cut-of drain current i onductance ( s during the t at the gate to witching speed Qg value, it wil the majority o alance atch has bee n in section al complicatio gate driver ci h the gate of Q te Resistor M e balancing in roblems that m ally driven by ge (VGS(TH)) wi flowing throu ff region whe is controlled gFS) characte transition from o turn-on the d of the MOS l turn on fast of the current en created an 3, the use ons, and it is rcuit shown in Q1. R3 is con Mismatch
n paralleled M may arise. y the same ga ll turn on fast ugh the MOS ere the MOSF by the gate-t eristics of the m on to off a MOSFET an SFET. When er than the re t during the tr nd tested to s of gate res critical to en n figure 1, Q1 nnected to R1
age 2 of 8
MOSFET ate driver ter than a FET with FET turns to-source e device. and vice- nd enable n multiple est of the ransition, show the sistors is sure that 1 and Q2 1 and the

Page 3
Rev. 1.0
Figures 2a a resistor mism gate resistan flow through larger voltage handling larg to balance cu in a parallele 2.3. The Effe In high-powe overall syste controlled. Figure 3 show In this circuit MOSFET tha
on Note M
Figure nd 2b show t match. Chann nce. These fa Q2. The hig e peaks and ger peak curre urrent through d application, ect of the Ga er, high-frequ em. Excessiv ws parasitic i , the drain ind at was chosen Fig
2a. Turn-On the gate-to-so nel 1 shows t aster switchin her current flo ringing. The ents during th h each MOSF , and using m te Driver Cir uency applica ve stray indu nductance in ductance of Q n for this simu gure 3. A Sim
Waveforms ource voltage the faster turn ng times provo ow through th e difference b he transitions FET during tr matching gate rcuit Layout o ations, the pa ctance in the two parallele Q1 is 40nH (L ulation. mulating Circ
Figu s during turn- n-on and turn oke higher cu he parasitic in between Q1 a due to the m ransitions to a resistance is on Voltage U arasitic induc e drain may c ed MOSFETs L1) and the in cuit with Diff ure 2b. Turn- -on and turn- n-off times of urrent flow thr nductance in t and Q2 in fig mismatched g avoid excessi the key to ac Unbalance ctance of the cause the M , intentionally ductance of Q ferent Drain I -Off Wavefor off that result Q1, the resu rough Q1, co the drain and gures 2a and ate driver res ive stress on chieving the d e PCB can n OSFET to fa y skewed to s Q2 is 20nH (L Inductance
rms t from the gat ult of the sligh mpared to th d source of Q 2b shows th sistors. It is i one of the M desired perfor negatively im ail if they are simulate a poo L2). AOT470
age 3 of 8
te driving htly lower e current 1 causes hat Q1 is mportant MOSFETs rmance. mpact the not well or layout. is a 75V

Page 4
Rev. 1.0
During turn-o and the chan parasitic ind approximatel When the pa term will be u higher drain shown in figu circuit. This MOSFET exc driver circuit designer can
3. Manag
Many design However, this even surpass
on Note M
Figu off a voltage w nging current uctance is o y the same. rasitic inducta unequal. This voltage on Q ure 4) is also combination ceed its maxi as shown in avoid these
ing Potent
ners tend to d s approach c s the maximu
Induc indu di/dt
ure 4. Simula will be added (V = L* di/dt) optimized for ances in the d s difference, i Q1. Additiona larger when n of ringing a imum rated d section 2.2, mismatches.
tial Oscillat
directly conne can easily cau m rated gate
ced by drain ctance and
tion Wavefo to the maxim ). If the matc each MOSF drains are diff in turn, influen ally, since the L1 rings with and the volta drain-to-sourc and minimizi
tions in Pa
ect both gates use an oscilla voltage and w
rms with Diff mum drain vo ching circuits FET, the ma ferent, the two nces the mag e drain induc h the Coss of age spike on e voltage and ng parasitic c
aralleled M
s and both d ation on the g wind up dama
Q1 current
fferent Drain ltage as dete consist of the x drain volta o excessive v gnitude of the ctance of Q1 the AOT470 the drain du d cause failur circuit inducta
rains togethe gate. Worst c aging the MO Inductances ermined by the e same di/dt age seen by voltages caus e di/dt and eve is larger, its and the para uring turn-off re. By carefu ance during P
er when paral case, the osc OSFET.
s e parasitic ind characteristic each device sed by the V = entually will re ringing ampl asitic resistan can easily m ully designing PCB layout, th
lleling two MO cillation ampli
age 4 of 8
ductance c and the e will be = L * di/dt esult in a itude (as nce in the make the the gate he circuit OSFETs. itude can

Page 5
Rev. 1.0
3.1. Example Figur Figure 5 sho together. Th oscillations o voltage or dra Through the result of add identical on t when paralle 3.2. Root Ca To understan connected to MOSFETs w These compo Resonan Quality fa
on Note M
es of Oscilla Figur re 6. Turn-Of ows a clear e he high freque often have ve ain-to-source use of individ ding a single the two MOS led. This gre ause Analysis nd the cause ogether, it is with the paras onents form a nt frequency o actor of a seri
tion re 5. Turn-Of ff Waveforms example of a ency oscillatio ery high amp voltage and dual gate driv resistor in t FETs, meani eatly improves s of Gate Os e of the high s important to sitic drain ind a low-impedan of a series RL ies RLC circu
ff Waveforms s of Two MO an oscillation on of ~150MH plitudes and damage the d ving resistors he gate of e ng that the cu s the reliability scillation h frequency o analyze th ductances, g nce loop and LC circuit ��
s of Two MO SFETs Paral that can occ Hz occurs du can easily e device. , the oscillatio each MOSFE urrent throug y of the circui oscillation at he equivalent ate capacitan can be consi
LC f
0 =
SFETs Direc lleled with Se cur when the ring the turn- exceed the m on can easily T. Both gat h each devic t. t the gate of t circuit. Fig nces (Cgd), idered as a se
��1�� ��2�� ctly Parallele eparate Driv two gates a -on and turn-o maximum rat y be removed te and drain e can be ass f two MOSF gure 7 show and gate res eries RLC eq
d ing Resistor are directly co off transitions ting of gate-t d. Figure 6 sh voltages are sumed to be t ETs that are ws the two p sistances all uivalent circu
age 5 of 8
rs onnected s. These to-source hows the e virtually the same e directly paralleled detailed. uit.

Page 6
Rev. 1.0
Equations 1 a that resonan selective a c amplitude. I which will he When two AO which in turn gate resistor gates, as sho The circuit si suppressing the AOT474 inductance o show in figur the effective
on Note M
and 2 determ t frequency. circuit behave n order to av lp to suppress OT474 power n increases th of 10Ω to th own in figure 6 mulation in fi oscillations. datasheet. of 60nH in th re 8a. Figure gate resistan
mine the reson The lower i es in respond void this osci s the oscillatio Figur r MOSFETs a he Q factor (Q he gate of ea 6. gures 8a, 8b The parame The device e loop, the n e 8b shows th ce from 5.6Ω
nant frequenc mpedance th ding to signa llation, equal on when the re 7. Model o are paralleled Q is inversely ach MOSFET and 9 furthe ters used in e��s internal R new equivale he impact of a Ω to 25.6Ω.
cy of the serie he circuit has ls of a given gate resisto loop impedan of Paralleling d, the oscillati y proportional to reduce th r demonstrate this model w Rg is 2.8Ω a nt circuit and adding a 10Ω es equivalent s, the higher n frequency, t rs are recom nce is very low g of MOSFET ion that resul to Cgd). The he Q factor a es why series ere obtained nd the Cgd i d the values Ω series gate circuit and th the resulting the higher th mmended in s w. Ts ts is due to th e solution is t nd suppress s gate resista from the ele s 36pF. As of the equiva resistor each
he quality fact Q factor. T he resulting o series with ea he reduced C to connect a the oscillatio ances are imp ctrical specifi ssuming the alent impeda MOSFET, in
age 6 of 8
tor (Q) at The more oscillation ach gate, Cgd value, separate on on the portant to ication of parasitic nces are ncreasing

Page 7
Rev. 1.0
Small-signal circuit model simulating th corresponds circuit in figur circuit is sign
on Note M
Figure 8 w analysis perf ls shown in f he circuit in nicely to the re 8b, showin ificantly reduc
a. RLC Circu ith Internal R formed using figures 8a an figure 8a sh waveform sh ng the impact ced, explainin Figure 9. Si
uit Model Rg the paramete nd 8b yielded ows the app hown in figure of adding a 1 ng the result s mulation Wa
Figur 10Ohm ers obtained the results s proximately 1 e 5. The blue 10Ω gate resi shown in figu aveforms of a re 8b. RLC C Resistor in S from the AOT shown in figu 50MHz reso e curve is the stor to each M re 6 of a very a Series RLC ircuit Model Series with t T474 datashe ure 9. The r onant frequen simulation re MOSFET gate y clean gate d C Circuit
with a the Gate eet and the e red curve obt ncy at high Q esult for the e e. The Q fac drive waveform
age 7 of 8
quivalent tained by Q, which quivalent tor of the m.

Page 8
Rev. 1.0
4. Conclu
For optimal c must be take and turn-off t in order to m parasitic indu
1. Parallelin J.B. Fors 2. Analysis QAIN Min 201804, C
© 2013 Alpha LEGAL DISCL Alpha and Om the information described here without further infringement o LIFE SUPPOR ALPHA AND O IN LIFE SUPP As used herein 1. Life support systems which the body or (b) failure to perfo instructions for reasonably exp user.
on Note M
current sharin en while desig times while re inimize curre uctance in hig
ng of MOSFE sythe, IEEE-IA of Power MO n, XU Ming-qi China, 2007.1
and Omega Se LAIMER mega Semicond n provided here ein. Alpha and r notice. This do f any third part RT POLICY OMEGA SEMIC PORT DEVICES n: t devices or sys h, (a) are intend ) support or sus orm when prope r use provided pected to resul
g and voltage gning the circ emoving the p nt loops while gh current pat Ts AS Conferenc OSFET Perfor ian, Min Zhi-n 11
emiconductor, ductor makes n ein and takes n Omega Semic ocument does ty��s intellectual CONDUCTOR S OR SYSTEM stems are devic ded for surgica stain life, and ( erly used in acc in the labeling lt in a significan www
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